This project has investigated the part of the SDS that is concerned
with Very High Definition Language (VHDL). A language used for specifying
electronics.
Currently, some of the VHDL code is created automatically but
the rest, the low level function bodies have to be generated by the user
textually. If the user is not familiar with the syntax of VHDL he may have
difficulty engineering this code. But, if he has a working knowledge of
programming and parallel concepts then he may be able to represent his ideas as
a diagram which could be parsed to produce the VHDL code.
This report will explain my solution, to what extent it solves this problem and what needs to be done to complete and extend its functionality.