Multiple Interrupts

Interrupt Vectors
Where is the interrupt service routine? (ISR). Various methodologies exist for establishing this. The simplest is to arrange that the ISR is always at the same address, or more likely a fixed address holds the address of the ISR. This way the system designer can locate the ISR anywhere in memory. For example, the 6805K1 can respond to three kinds of interrupt, these can be caused by the internal timer, an external event, or via software (SWI instruction). The address of the timer interrupt service routine must be stored at memory location 03F8, that of the external ISR must be at 03FA, while 03FB holds the address of the SWI routine. Many other microprocessors, including the 6809 and 6502  operate in a similar way. A more sophisticated scheme is implemented in some microprocessors (eg the  Z80)  where one of the options available is for the interrupting device to provide a vector, this vector is combined with a special purpose register called the Interrupt Vector register (IV). The result is used to address a table of ISR addresses. The 68000 family of microprocessors can do this too.

This technique of the interrupting device effectively providing the address of its service routine saves time when there may be many sources of interrupts. Otherwise, when more than one device can generate interrupts some scheme must be established to identify which device is generating the interrupt. The simplest (though rarely used) scheme is to provide separate interrupt connections for each device. A neater approach is to WIRE-OR the interrupt lines from each device together. In such a scheme the processor, on receipt of an interrupt must poll all of the devices to establish which has generated the interrupt. This technique is slow so time critical devices will be examined first, the concept of time critical devices introduces the notion of interrupt priorities - clearly some devices are more important than others. A daisy chain arrangement of devices facilitates a prioritized connection of multiple devices and can also eliminate the polling problem.

All of the devices in the chain have an interrupt enable input and an interrupt enable output as well as an interrupt request output and interrupt acknowledge input. With no interrupts pending, the interrupt input is effectively connected through to the output so a logic one propagates down the chain.

When a device generates an interrupt its INTRQ lines and IEO lines go low, signalling an interrupt to the CPU with the former and disabling subsequent devices in the chain with the latter.The CPU acknowledges the request by taking INTAK low - signalling to the device that it may place its vector onto the data bus. The ability to disable devices lower in the chain means that a priority scheme is hardwired into the daisy chain. The notion of prioritizing interrupts is important as it is conceivable that interrupts may occur (or at least appear to) simultaneously, though more likely it may be desirable to nest interrupts; we might consider the software in a computer to consist of numerous different programs, the importance of these programs is obviously variable. For instance we might anticipate that a low speed printer requesting service might be considered less important than an interrupt signalling that a power failure is imminent - so it is reasonable that the latter should take priority over the former (and therefore be able to interrupt it) but not vice-versa. This is a slightly extreme example and quite often there may be a number of devices with similar or equal importance, or circumstances may arise when priorities change. In such cases the daisy chain approach falls down as priorities can only be re-arranged by re-wiring. Clearly if priorities are determined in software they are easier to change. Some processors can combine both schemes to produce a two dimensional prioritization.

In cases where many devices are equally important a scheme must be devised so that all devices are serviced equally. One way to achieve this is to use a rotating priority scheme whereby the highest priority device, after being serviced becomes the lowest priority device - thus all devices get a look in.